Conventionally, three forms of memory addresses are used for referencing program instructions and data stored in the memory of a computer: relative, symbolic and absolute. Relative addresses describe memory locations relative to a base or reference memory location. Symbolic addresses are arbitrary names or labels used for mnemonically referencing memory locations. Prior to program loading and execution, symbolic addresses are translated into relative, relocatable memory addresses which are instantiated using a symbol to a base or reference memory location. Absolute addresses are actual physical memory locations hard-coded into the program.
During the translation of source code to object code, the code generator of the compiler (or equivalent translator) outputs relocatable machine code. The code generator inserts a code sequence into the code for generating the absolute address of each relocatable address at runtime. The code sequence can also be expressed in assembly language and manually programmed into assembly language programs.
The particular code sequence used for generating memory addresses is determined by two factors: the architecture of the particular computer upon which the code is to be run and the code model desired for the code. The architecture dictates hardware-based considerations, such as the address space, number of bits per address and the registers available for address formation and calculation. The code model defines the addressability properties given the constrains of the architecture. The two basic classes of code models are absolute and position independent. Absolute code models vary in the number of bits that are settable within each address. Position independent code models employ an offset stored in a register or use some form of indirect addressing.
In general, architectures employing an absolute code model for accessing the full address space require code sequences for providing general addressing. For instance, with a 32-bit architecture, code sequences that can generate any 32-bit absolute address within the full address space are generally used. An example of a 32-bit architecture employing such a linear, 32-bit address space is the SPARC.TM. chip architecture, version 8, such as described in "The SPARC Architecture Manual, Version 8," chs. 1 and 6 and Apps. J and K, SPARC Int'l, Inc. (1992), the disclosure of which is incorporated herein by reference. SPARC.TM. is a trademark of SPARC International, Inc., Menlo Park, Calif. Normally, each code sequence can generate any one of the addresses for the 32-bit address space by filling in constants in the relocatable machine code identified by the address symbols. The link-editor fills in these constants after compilation since the values of the constants are unknown beforehand.
Similarly, with a 64-bit architecture, the natural extension of the 32-bit absolute address is the 64-bit absolute address. An example of a 64-bit architecture employing such a linear, 64-bit address space is the SPARC.TM. chip architecture, version 9 (SPARC V9), such as described in "The SPARC Architecture Manual, Version 9," chs. 1 and 8 and Apps. D and J, SPARC Int'l, Inc. (1994), the disclosure of which is incorporated herein by reference. However, the conventional code sequences used to generate 64-bit absolute addresses are relatively long and slow. For example, with the SPARC V9 chip architecture, the code sequence used to access the full address space requires six instructions. Absent code optimization, this entire six-instruction code sequence must be executed each time an access to memory is issued. Consequently, any decrease in the number of instructions required in the code sequence would normally result in a significant performance increase. Moreover, not every program needs to use full 64-bit absolute addresses and a code model defining an intermediate size between 32 and 64 bits can create a useful subset with increased memory access performance.
Therefore, there is a need for an approach to providing absolute addressing for an intermediate code model as a subset of a larger address space. Such an approach would provide the benefit of faster and smaller code while still allowing absolute addressing of a significantly larger address space than available in an architecture offering a comparatively smaller maximum address space.
There is a further need for an efficient code sequence used for providing absolute addressing into a subset of a full address space whereby the code sequence is faster and smaller than the code sequence used for providing absolute addressing into the full address space.